BMBF-Research Project "VerSiPlektor"

Integration assistent for physical design of vertical heterogenious System-in-Packages (SiP)

Vertical Integration of elektronic components into a Package (System-in-Package, SiP) is one of the future oriented developments for modern microelectronics. in this project the required methodologies shal be found for technology correct design based on algorithmn for vertical integrated systems. Its integration into currectly existing eCAD toold shall be done for production and technology specific constraints.

Formulation and solving the optimized 2D placement based on a mathematical solution is a non-trivial task and it will be even a bigger chalenge to extend this task to complex 3D applications with all its contraints.

The VerSiPlekktor research project was started on Nov. 1st 2006 and shaal deliver results on Sep 30th 2009. The results shall lead to a sellable product after the project ends.